; file: macross.inc
; 
; started 20070715 poly@omino.com
; was 12f509, now for 16f628 also.
; --------------------------------------------
; these generally follow
; conventions similar to the standard opcodes.
; it is generally assumed that the W and STATUS
; registers are affected
; ---------------------------------------------

MOVLF	MACRO	v,freg
	MOVLW	v
	MOVWF	freg
	ENDM

ADDLF	MACRO	v,freg
	MOVLW	v
	ADDWF	freg,f
	ENDM

ADDFF	MACRO fregsrc,fregdst
	MOVFW	fregsrc
	ADDWF	fregdst,f
	ENDM

SUBFF	MACRO fregsrc,fregdst
	MOVFW fregsrc
	SUBWF fregdst,f
	ENDM

MOVFF	MACRO fregsrc,fregdst
	MOVFW	fregsrc
	MOVWF	fregdst
	ENDM

; simplifications of common "skip" functions
IFZ	MACRO
	BTFSC	STATUS,Z
	ENDM

IFNZ MACRO
	BTFSS	STATUS,Z
	ENDM

IFC	MACRO
	BTFSC	STATUS,C
	ENDM

IFNC MACRO
	BTFSS	STATUS,C
	ENDM

IFBC MACRO _reg,_bit
	BTFSS	_reg,_bit
	ENDM

IFBS MACRO _reg,_bit
	BTFSC	_reg,_bit
	ENDM


; Decrement a file register unless it's
; already at zero. 3 cycles every time.
DECFPIN	MACRO	freg
	INCF	freg,f
	DECFSZ	freg,f
	DECF	freg,f
	ENDM

; Increment or decrement a file register
; to bring it closer to the destination.
; already there? no change.
; 8 cycles & 8 instructions exactly.
; no gotos.
MIGFPIN MACRO	fregcur,fregdst
	MOVFW	fregcur
	SUBWF	fregdst,w
	MOVLW	1		; assume increment
	IFNC
	MOVLW	0xff	; negative sub, so decrement
	IFZ
	MOVLW	0		; oh, they were equal
	ADDWF	fregcur,f
	ENDM

; insert a handful of NOPs, as many as you ask for.
NOPS	MACRO	cycles
_delay_k SET cycles
		WHILE _delay_k > 0
_delay_k SET _delay_k - 1
		NOP
		ENDW
		ENDM

; fetch one of our indirect registers to W
MOVIW MACRO _iReg
	MOVLF _iReg,FSR
	MOVFW INDF
	CLRF FSR  ; otherwise upper bits affect MOVs
	ENDM

MOVIF MACRO _iReg,_reg
	MOVIW _iReg
	MOVWF _reg
	ENDM

MOVFI MACRO _reg,_iReg
	MOVFW _reg
	MOVWI _iReg
	ENDM

BANK0 MACRO
	BCF		STATUS,RP0	; Select Bank 0
	BCF		STATUS,RP1	; Select Bank 0
	ENDM
BANK1 MACRO ;assumes from bank 0.
	BSF		STATUS,RP0	; Select Bank 1
	ENDM

CopyBit	MACRO	sourceReg,sourceBit,destReg,destBit
	IFBS	sourceReg,sourceBit
	 BSF	destReg,destBit
	IFBC	sourceReg,sourceBit
	 BCF	destReg,destBit
	ENDM



; Poke a random value into a file register
; mask is anded, and min is added
; RANDF x,31,10 to get 10..41
; 11c + 1 if mask != 0xff + 2 if min != 0
; 
RANDF MACRO	fregdst,mask,min
	CALL	Rnd
	MOVFW	rnd
	
	IF mask != 0xff
	ANDLW	mask
	ENDIF

	MOVWF	fregdst

	IF min != 0
	MOVLW	min
	ADDWF	fregdst,f
	ENDIF

	ENDM

; Interrupt Helpers
IntStart MACRO _wTemp,_statusTemp
	; _wTemp & _statusTemp MUST be in a bank-shared location, like 70-7f
	MOVWF	_wTemp	; Copy W to a Temporary Register regardless of current bank
	SWAPF STATUS,W ; Swap STATUS nibbles and place into W register
	MOVWF _statusTemp ; Save STATUS to a Temporary register
	ENDM

IntFinish MACRO _wTemp,_statusTemp
	SWAPF	_statusTemp,W ; Swap original STATUS register value into W (restores original bank)
	MOVWF	STATUS ; Restore STATUS register from W register
	SWAPF	_wTemp,F ; Swap W_Temp nibbles and return value to W_Temp
	SWAPF _wTemp,W ; Swap W_Temp to W to restore original
	RETFIE
	ENDM